The present invention relates to a cache control system utilizing a cache memory for an instruction cache memory and/or a data cache memory or commonly for instructions and data and, more particularly, to a technology which is effective if applied to a data processor or a microcomputer system utilizing such cache memory packaged in or attached to the outside thereof.
As a method for improving the processing ability of a central processing unit, a cache memory, which has a lower capacity but can access instructions or data at a higher speed than an external large-capacity memory (e.g., RAM/ROM, a hard disc unit or a floppy disc drive unit) and which is used for reading the information of the external memory partially. Such central processing unit can continue the data processing while referring to the instructions or data in the cache memory while the information is present in the cache memory, so that the data processing ability can be drastically improved better than the executions while accessing to the external large capacity memory. If, however, none of the information demanded by the central processing unit is present, the cache memory interrupts the execution of instructions by the central processing unit to read and latch the necessary information from the external large capacity memory and then reopens the interrupted data processing of the central processing unit. If this state frequently occurs, the central processing unit has its performance dropped substantially. In order to maximize the performance of the central processing unit, therefore, the necessary information always has to be present in the cache memory during the execution so as to eliminate the interruption of the instruction execution.
The engineer designing a system by using the central processing unit is well acquainted with the fact that the result of a benchmark indexing the performance highly depends upon the capacity of a cache memory (of packaged and/or outside ones) or its control method, and the capacity and method of the cache memory are one of important points of selection for adopting the central processing unit. In a design stressing the performance, the cache memory control is carried out in the LSI, and the high speed memory of relatively high capacity is connected as the cache memory with the outside of the LSI. In the design stressing the system cost, on the other hand, the system is designed at a low cost with a small number of parts, so that a single-chip microcomputer is given a high performance and a compact construction by packaging the cache memory (and a peripheral device such as a communication port or timer) in the LSI.
The high speed processor having the cache memory packaged therein is described, for example, in "ADJ-602-065 of Section 6 Cache" of pp. 83 to 85 of "Temporary Version of Hitachi 32-bit RISC Processor PA/10 HD69010 Hardware Manual". This cache memory is equipped with a plurality of cache lines. Each cache line is composed of: a cache tag for storing a valid address (or virtual address or physical address) indicating which position (or address) of the external memory is corresponded to by the information latched by the cache line; a data portion for storing the information of consecutive n-words (e.g., four words) headed by the valid address; and a valid bit indicating whether or not the information stored in the cache line is valid.
The aforementioned cache memory has a "fetch" operation for the data processor or central processing unit to read instruction in accordance with an instruction executing procedure and a "line fetch" to read a valid instruction from the external memory if no valid instruction is present in the cache memory. Specifically, the instruction fetch control unit decides whether or not a valid information is present in the instruction cache memory, on the basis of the instruction address from the central processing unit and the information of the cache tag in the instruction cache memory, and controls the fetch of the central processing unit and the line fetch to read a valid instruction automatically from the external memory. Incidentally, the instruction fetch control unit is operated by the packaged control program or control logic in accordance with the specifications which are independent from the instruction control of the program and intrinsic to the LSI, so as to speed up the operations.
If no valid information is present in the cache memory during the instruction execution, the central processing unit has to interrupt it temporarily till a valid information is read from the external memory by the line fetch. This execution interruption period is called the "mishit penalty", which influences the drop of the system performance as the operating speed of the central processing unit is drastically accelerated to extend the difference in the access time from the external memory. Thus, there has been positively carried out the (prefetch) method of reading the information, which is expected to be used in the future by the central processing unit, in advance to the execution by the central processing unit. For example, the instruction prefetch is controlled by the instruction fetch control unit and is operated substantially like the line fetch except that the expected address is used.